The invention relates to computer systems in general and, more specifically, to a method and apparatus for caching data in a computer system.
As it is known in the art, a computer system generally includes a Central Processing Unit (CPU) for processing instructions, as well as a main memory device which is used to store data processed by the instructions. Due to the latency inherent in obtaining data from the memory devices, often a RAM device which is smaller and faster than main memory, called a Cache RAM, is provided between the CPU and the memory device.
The Cache RAM is used to store subsets, or blocks, of data from memory that may be used quickly and efficiently by the Central Processing Unit for processing the instruction sets, without incurring the time delay associated with accessing main memory.
Generally, the Cache RAM is external to the Central Processing Unit. However, as technology has advanced and integrated circuit devices are able to include more logic, a Cache RAM has been provided within the CPU integrated circuit device. Thus, access time for obtaining data from a RAM device is further reduced, because the time delay associated with accessing a RAM device outside of the integrated circuit is eliminated. The RAM device which is included in the integrated circuit is generally referred to as a primary cache.
However, although having a primary cache on the integrated circuit greatly reduces the latency for receiving data in the cache, because the cache is located on the integrated circuit it is a fixed size. Thus, when the CPU needs data that is not in the cache, it must access a memory device external to the integrated circuit device. One approach is to provide a separate cache which is larger than the primary cache yet smaller and faster than main memory in the system design. This separate cache is generally referred to as a secondary cache.
One problem associated with including a secondary cache is that generally the main memory, the secondary cache and the primary cache all need a separate memory controller. In addition, an arbitration device is required between the three controllers to ensure that the data in each remains coherent. This arbitration is often complex and prone to design error.
A second drawback of including both a secondary cache and main memory is due to the width of the data busses which couples the integrated circuit to the secondary cache and main memory.
Due to the desire for improved performance of computer systems, a 64 bit architecture has been implemented in the CPU designs. By providing a wider data bus, the CPUs are able to receive twice the amount of data per memory access (as opposed to that received on a 32 bit bus) and thus can process data faster and more efficiently. As a result of using the 64 bit architecture, however, the busses connecting the secondary cache to the integrated circuit and the main memory to the integrated circuit each include 64 bits of data as well as parity bits and separate address busses. Thus, the amount of pins used in accessing external memory devices alone uses a large portion of the available pins of the integrated circuit device. Because there are I/O devices, ROMs, and other devices which also require interface pins of the CPU integrated circuit, design tradeoffs must often be made between improving system performance by including a secondary cache or increasing the package size (and consequently the cost and area) of the CPU device to increase the number of available I/O pins.